XC5VLX50-1FFG676C

Product Summary

The XC5VLX50-1FFG676C is an FPGA. It is available in -3, -2, -1 speed grades, with -3 having the highest performance. The XC5VLX50-1FFG676C’s DC and AC characteristics are specified for both commercial and industrial grades. Except the operating temperature range or unless otherwise noted, all the DC and AC electrical parameters of the XC5VLX50-1FFG676C are the same for a particular speed grade (that is, the timing characteristics of a -1 speed grade industrial device are the same as for a -1 speed grade commercial device). However, only selected speed grades and/or devices might be available in the industrial range. All supply voltage and junction temperature specifications are representative of worst-case conditions. The parameters of the XC5VLX50-1FFG676C included are common to popular designs and typical applications.

Parametrics

XC5VLX50-1FFG676C absolute maximum ratings: (1)VCCINT, Internal supply voltage relative to GND: –0.5 to 1.1 V; (2)VCCAUX, Auxiliary supply voltage relative to GND: –0.5 to 3.0 V; (3)VCCO, Output drivers supply voltage relative to GND: –0.5 to 3.75 V; (4)VBATT, Key memory battery backup supply: –0.5 to 4.05 V; (5)VREF, Input reference voltage: –0.5 to 3.75 V; (6)VIN, 3.3V I/O input voltage relative to GND: –0.75 to 4.05 V; 2.5V or below I/O input voltage relative to GND: –0.75 to VCCO + 0.5 V; (7)VTS, Voltage applied to 3-state 3.3V output: –0.75 to 4.05 V; Voltage applied to 3-state 2.5V or below output (user and dedicated I/Os): –0.75 to VCCO + 0.5 V; (8)TSTG Storage temperature (ambient): –65 to 150℃; (9)TSOL Maximum soldering temperature: +220℃; (10)TJ Maximum junction temperature: +125℃.

Features

XC5VLX50-1FFG676C features: (1)In-System Programmable PROMs for Configuration of Xilinx FPGAs; (2)Low-Power Advanced CMOS NOR FLASH Process; (3)Endurance of 20,000 Program/Erase Cycles; (4)Operation over Full Industrial Temperature Range (–40 to +85℃); (5)IEEE Standard 1149.1/1532 Boundary-Scan (JTAG) Support for Programming, Prototyping, and Testing; (6)JTAG Command Initiation of Standard FPGA Configuration; (7)Cascadable for Storing Longer or Multiple Bitstreams; (8)Dedicated Boundary-Scan (JTAG) I/O Power Supply (VCCJ) ; (9)I/O Pins Compatible with Voltage Levels Ranging From 1.5V to 3.3V ; (10)Design Support Using the Xilinx Alliance ISE and Foundation ISE Series Software Packages.

Diagrams