RTL8212-GR

Product Summary

The RTL8212/RTL8212N/8211N integrate dual/single independent Gigabit Ethernet
transceivers into a single IC and performs all the physical layer (PHY) functions for
10Base-T, 100Base-TX, and 1000Base-T Ethernet on category 3 (10Base-T) or category 5
UTP cable (except 1000Base-T half duplex operation).
The device includes the PCS, PMA, and PMD sub-layers. They perform
encoding/decoding, clock/data recovery, digital adaptive equalization, echo cancellers,
cross-talk elimination, line driver, as well as all other required support circuit functions.
The device also integrates an internal hybrid that allows the use of inexpensive 1:1
transformer modules.
Each of the two independent transceivers features an industrial standard GMII, MII, and
RGMII (Reduced Gigabit Media Independent Interface). To further reduce PCB trace
complexity, the RTL8211N/8212N also provides an innovative 2.5Gbps serial interface 鈥?
the Reduced Serial Gigabit Media Independent Interface (RSGMII). Both dual
transceivers can simultaneously communicate with the MAC through the same RSGMII
interface.
The RTL8212/RTL8212N/8211N adopts mixed mode 0.13渭m CMOS technology and
analog line driver architecture that offers lower power consumption than DAC
architecture.
Two package types are available; a thermally-enhanced 128-pin EDHS-QFP (Exposed
Drop-in Heat Sink QFP) package, and a QFN (Quad Flat No-Lead) 76-pin package.

Features

魛倓 Single/Dual integrated 10/100/1000Base-T Gigabit Ethernet transceiver
魛倓 Supports full duplex at 10/100/1000Mbps, and half duplex at 10/100Mbps
魛倓 Supports 2.5V I/O (3.3V input tolerance) GMII and RGMII interfaces in 10/100/1000
mode for RTL8212 (QFP-128 Package)
魛倓 Supports RSGMII (2.5Gbps serial high speed interface) in 10/100/1000 mode for
RTL8212N and RTL8211N (QFN-76 Package)
魛倓 Crossover detection and auto correction at all 3 speeds
魛倓 Automatic detection and correction of wiring pair swaps, pair skew, and pair polarity
魛倓 Supports serial LED mode
魛倓 Line driver architecture with low power dissipation PAVE= 0.78W/port
魛倓 3.3V, 1.8V, and 1.2V power supply (2.5V is generated by internal linear regulator for
Digital I/O pads)
魛倓 Packages:
魛倠 EDHS QFP-128, 14x20mm, 0.5mm lead pitch package
魛倠 QFN-76, 9x9mm, 0.4mm pitch package
魛倓 0.13渭m CMOS process