EPM7256AEQC208-10

208-PQFP, Programmable Logic device, –0.5 to 4.6 V

Rated 5 Rating 5 | reviews | Write a review

Price:: US $13.00~15.00 / piece [Get Latest Price]

Reference price:

Qty (lots)	Price/lot
	US $13.00~15.00

PartNumber:: EPM7256AEQC208-10

Brand:: Altera Corporation - ALTR | Pack: QFP | D/C: 12+

Availability:: Supply Ability: 10000/Week Can Ship Immediately
Delivery: 10-15 Business Days (ships out within 3 Business days)

Quantity:: piece

Total Price:: US $0

Place Order via Escrow Service

Sold By

Mr. fisher's store

(China (Mainland))

add to my favourite

100% Positive feedback

Detailed seller ratings

Visit Store

Contact Now

Esrcow Service

Place orders confidently and securely via it

Safe payments
Quick and easy transactions
Free service charges

Learn More >>

Previous Next

Products Upload time: 2012-05-03

From Other Seller

Part Number:EPM7256AEQC208-10
US $13.00 - 15.00
AT25256AW-10SU-2.7

US $0.65 - 1.50 / Piece
(0) Remove
HEF4093BT

US $0.15 - 1.20 / Piece
(0) Remove
Quantity:

piece

Product Summary

The EPM7256AEQC208-10 is a high-density, high performance Programmable Logic device which based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EPM7256AEQC208-10 operates with a 3.3-V supply voltage and provide 600 to 10,000 usable gates, ISP, pin-to-pin delays as fast as 4.5 ns, and counter speeds of up to 227.3 MHz.

Parametrics

EPM7256AEQC208-10 absolute maximum ratings: (1)Supply voltage With respect to ground: –0.5 to 4.6 V; (2)DC input voltage: –2.0 to 5.75 V; (3)DC output current, per pin: –25 to 25 mA; (4)Storage temperature No bias: –65 to 150 ℃; (5)Ambient temperature Under bias: –65 to 135 ℃; (6)Junction temperature BGA, FineLine BGA, PQFP, and packages, under bias: 135 ℃.

Features

EPM7256AEQC208-10 features: (1)Built-in boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1; (2)Supports JEDEC Jam Standard Test and Programming Language (STAPL) JESD-71; (3)Enhanced ISP features: Enhanced ISP algorithm for faster programming (excluding EPM7128A and EPM7256A devices), ISP_Done bit to ensure complete programming (excluding; (4)EPM7128A and EPM7256A devices), Pull-up resistor on I/O pins during in-system programming; (5)Pin-compatible with the popular 5.0-V MAX 7000S devices; (6)High-density PLDs ranging from 600 to 10,000 usable gates; (7)Extended temperature range.